Technologies for structured database query

ABSTRACT

Technologies for determining set membership include a computing device that further includes one or more accelerator devices. Each accelerator device is to receive input data and definition table configuration data, the input data including a packed unsigned integers of column data from database and the definition table configuration data including a set membership query condition, generate a definition table indicative of element values that satisfy the set membership query condition, generate a lookup request for an element of the column data of the input data, perform the lookup request by accessing the definition table to determine whether the element satisfies the set membership query condition, and generate output indicative of whether the element is a member of the set membership.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims the benefit of Indian Provisional PatentApplication No. 201741030632, filed Aug. 30, 2017, and U.S. ProvisionalPatent Application No. 62/584,401, filed Nov. 10, 2017.

BACKGROUND

Set membership queries are typically performed by processors of acomputing device to determine whether a query value is an element of aset that satisfies a set membership query condition. The set membershipqueries are often used to filter large database columns to obtain a setof elements that satisfies a set membership query condition. However,processor-based implementations may require consumption of large amountsof power and other resources due to the amount of data that is requiredto be read into the processors.

Modern computing devices may include general-purpose processor cores aswell as a variety of hardware accelerators for performing specializedtasks. Certain computing devices may include one or more acceleratorsembodied as field-programmable gate arrays (FPGAs), which may includeprogrammable digital logic resources that may be configured by the enduser or system integrator.

BRIEF DESCRIPTION OF THE DRAWINGS

The concepts described herein are illustrated by way of example and notby way of limitation in the accompanying figures. For simplicity andclarity of illustration, elements illustrated in the figures are notnecessarily drawn to scale. Where considered appropriate, referencelabels have been repeated among the figures to indicate corresponding oranalogous elements.

FIG. 1 is a diagram of a conceptual overview of a data center in whichone or more techniques described herein may be implemented according tovarious embodiments;

FIG. 2 is a diagram of an example embodiment of a logical configurationof a rack of the data center of FIG. 1;

FIG. 3 is a diagram of an example embodiment of another data center inwhich one or more techniques described herein may be implementedaccording to various embodiments;

FIG. 4 is a diagram of another example embodiment of a data center inwhich one or more techniques described herein may be implementedaccording to various embodiments;

FIG. 5 is a diagram of a connectivity scheme representative oflink-layer connectivity that may be established among various sleds ofthe data centers of FIGS. 1, 3, and 4;

FIG. 6 is a diagram of a rack architecture that may be representative ofan architecture of any particular one of the racks depicted in FIGS. 1-4according to some embodiments;

FIG. 7 is a diagram of an example embodiment of a sled that may be usedwith the rack architecture of FIG. 6;

FIG. 8 is a diagram of an example embodiment of a rack architecture toprovide support for sleds featuring expansion capabilities;

FIG. 9 is a diagram of an example embodiment of a rack implementedaccording to the rack architecture of FIG. 8;

FIG. 10 is a diagram of an example embodiment of a sled designed for usein conjunction with the rack of FIG. 9;

FIG. 11 is a diagram of an example embodiment of a data center in whichone or more techniques described herein may be implemented according tovarious embodiments;

FIG. 12 is a simplified block diagram of at least one embodiment of acomputing device for determining set membership;

FIG. 13 is a simplified block diagram of at least one embodiment of anenvironment that may be established by an accelerator of the computingdevice of FIG. 12; and

FIGS. 14 and 15 are a simplified flow diagram of at least one embodimentof a method for determining set membership that may be executed by theaccelerator of FIGS. 12 and 13.

DETAILED DESCRIPTION OF THE DRAWINGS

While the concepts of the present disclosure are susceptible to variousmodifications and alternative forms, specific embodiments thereof havebeen shown by way of example in the drawings and will be describedherein in detail. It should be understood, however, that there is nointent to limit the concepts of the present disclosure to the particularforms disclosed, but on the contrary, the intention is to cover allmodifications, equivalents, and alternatives consistent with the presentdisclosure and the appended claims.

References in the specification to “one embodiment,” “an embodiment,”“an illustrative embodiment,” etc., indicate that the embodimentdescribed may include a particular feature, structure, orcharacteristic, but every embodiment may or may not necessarily includethat particular feature, structure, or characteristic. Moreover, suchphrases are not necessarily referring to the same embodiment. Further,when a particular feature, structure, or characteristic is described inconnection with an embodiment, it is submitted that it is within theknowledge of one skilled in the art to effect such feature, structure,or characteristic in connection with other embodiments whether or notexplicitly described. Additionally, it should be appreciated that itemsincluded in a list in the form of “at least one A, B, and C” can mean(A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).Similarly, items listed in the form of “at least one of A, B, or C” canmean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).

The disclosed embodiments may be implemented, in some cases, inhardware, firmware, software, or any combination thereof. The disclosedembodiments may also be implemented as instructions carried by or storedon a transitory or non-transitory machine-readable (e.g.,computer-readable) storage medium, which may be read and executed by oneor more processors. A machine-readable storage medium may be embodied asany storage device, mechanism, or other physical structure for storingor transmitting information in a form readable by a machine (e.g., avolatile or non-volatile memory, a media disc, or other media device).

In the drawings, some structural or method features may be shown inspecific arrangements and/or orderings. However, it should beappreciated that such specific arrangements and/or orderings may not berequired. Rather, in some embodiments, such features may be arranged ina different manner and/or order than shown in the illustrative figures.Additionally, the inclusion of a structural or method feature in aparticular figure is not meant to imply that such feature is required inall embodiments and, in some embodiments, may not be included or may becombined with other features.

FIG. 1 illustrates a conceptual overview of a data center 100 that maygenerally be representative of a data center or other type of computingnetwork in/for which one or more techniques described herein may beimplemented according to various embodiments. As shown in FIG. 1, datacenter 100 may generally contain a plurality of racks, each of which mayhouse computing equipment comprising a respective set of physicalresources. In the particular non-limiting example depicted in FIG. 1,data center 100 contains four racks 102A to 102D, which house computingequipment comprising respective sets of physical resources (PCRs) 105Ato 105D. According to this example, a collective set of physicalresources 106 of data center 100 includes the various sets of physicalresources 105A to 105D that are distributed among racks 102A to 102D.Physical resources 106 may include resources of multiple types, suchas—for example—processors, co-processors, accelerators, fieldprogrammable gate arrays (FPGAs), memory, and storage. The embodimentsare not limited to these examples.

The illustrative data center 100 differs from typical data centers inmany ways. For example, in the illustrative embodiment, the circuitboards (“sleds”) on which components such as CPUs, memory, and othercomponents are placed for increased thermal performance. In particular,in the illustrative embodiment, the sleds are shallower than typicalboards. In other words, the sleds are shorter from the front to theback, where cooling fans are located. This decreases the length of thepath that air must to travel across the components on the board.Further, the components on the sled are spaced further apart than intypical circuit boards, and the components are arranged to reduce oreliminate shadowing (i.e., one component in the air flow path of anothercomponent). In the illustrative embodiment, processing components suchas the processors are located on a top side of a sled while near memory,such as DIMMs, are located on a bottom side of the sled. As a result ofthe enhanced airflow provided by this design, the components may operateat higher frequencies and power levels than in typical systems, therebyincreasing performance. Furthermore, the sleds are configured to blindlymate with power and data communication cables in each rack 102A, 102B,102C, 102D, enhancing their ability to be quickly removed, upgraded,reinstalled, and/or replaced. Similarly, individual components locatedon the sleds, such as processors, accelerators, memory, and data storagedrives, are configured to be easily upgraded due to their increasedspacing from each other. In the illustrative embodiment, the componentsadditionally include hardware attestation features to prove theirauthenticity.

Furthermore, in the illustrative embodiment, the data center 100utilizes a single network architecture (“fabric”) that supports multipleother network architectures including Ethernet and Omni-Path. The sleds,in the illustrative embodiment, are coupled to switches via opticalfibers, which provide higher bandwidth and lower latency than typicaltwisted pair cabling (e.g., Category 5, Category 5e, Category 6, etc.).Due to the high bandwidth, low latency interconnections and networkarchitecture, the data center 100 may, in use, pool resources, such asmemory, accelerators (e.g., graphics accelerators, FPGAs, ASICs, etc.),and data storage drives that are physically disaggregated, and providethem to compute resources (e.g., processors) on an as needed basis,enabling the compute resources to access the pooled resources as if theywere local. The illustrative data center 100 additionally receivesutilization information for the various resources, predicts resourceutilization for different types of workloads based on past resourceutilization, and dynamically reallocates the resources based on thisinformation.

The racks 102A, 102B, 102C, 102D of the data center 100 may includephysical design features that facilitate the automation of a variety oftypes of maintenance tasks. For example, data center 100 may beimplemented using racks that are designed to be robotically-accessed,and to accept and house robotically-manipulatable resource sleds.Furthermore, in the illustrative embodiment, the racks 102A, 102B, 102C,102D include integrated power sources that receive a greater voltagethan is typical for power sources. The increased voltage enables thepower sources to provide additional power to the components on eachsled, enabling the components to operate at higher than typicalfrequencies.

FIG. 2 illustrates an exemplary logical configuration of a rack 202 ofthe data center 100. As shown in FIG. 2, rack 202 may generally house aplurality of sleds, each of which may comprise a respective set ofphysical resources. In the particular non-limiting example depicted inFIG. 2, rack 202 houses sleds 204-1 to 204-4 comprising respective setsof physical resources 205-1 to 205-4, each of which constitutes aportion of the collective set of physical resources 206 comprised inrack 202. With respect to FIG. 1, if rack 202 is representative of—forexample—rack 102A, then physical resources 206 may correspond to thephysical resources 105A comprised in rack 102A. In the context of thisexample, physical resources 105A may thus be made up of the respectivesets of physical resources, including physical storage resources 205-1,physical accelerator resources 205-2, physical memory resources 205-3,and physical compute resources 205-4 comprised in the sleds 204-1 to204-4 of rack 202. The embodiments are not limited to this example. Eachsled may contain a pool of each of the various types of physicalresources (e.g., compute, memory, accelerator, storage). By havingrobotically accessible and robotically manipulatable sleds comprisingdisaggregated resources, each type of resource can be upgradedindependently of each other and at their own optimized refresh rate.

FIG. 3 illustrates an example of a data center 300 that may generally berepresentative of one in/for which one or more techniques describedherein may be implemented according to various embodiments. In theparticular non-limiting example depicted in FIG. 3, data center 300comprises racks 302-1 to 302-32. In various embodiments, the racks ofdata center 300 may be arranged in such fashion as to define and/oraccommodate various access pathways. For example, as shown in FIG. 3,the racks of data center 300 may be arranged in such fashion as todefine and/or accommodate access pathways 311A, 311B, 311C, and 311D. Insome embodiments, the presence of such access pathways may generallyenable automated maintenance equipment, such as robotic maintenanceequipment, to physically access the computing equipment housed in thevarious racks of data center 300 and perform automated maintenance tasks(e.g., replace a failed sled, upgrade a sled). In various embodiments,the dimensions of access pathways 311A, 311B, 311C, and 311D, thedimensions of racks 302-1 to 302-32, and/or one or more other aspects ofthe physical layout of data center 300 may be selected to facilitatesuch automated operations. The embodiments are not limited in thiscontext.

FIG. 4 illustrates an example of a data center 400 that may generally berepresentative of one in/for which one or more techniques describedherein may be implemented according to various embodiments. As shown inFIG. 4, data center 400 may feature an optical fabric 412. Opticalfabric 412 may generally comprise a combination of optical signalingmedia (such as optical cabling) and optical switching infrastructure viawhich any particular sled in data center 400 can send signals to (andreceive signals from) each of the other sleds in data center 400. Thesignaling connectivity that optical fabric 412 provides to any givensled may include connectivity both to other sleds in a same rack andsleds in other racks. In the particular non-limiting example depicted inFIG. 4, data center 400 includes four racks 402A to 402D. Racks 402A to402D house respective pairs of sleds 404A-1 and 404A-2, 404B-1 and404B-2, 404C-1 and 404C-2, and 404D-1 and 404D-2. Thus, in this example,data center 400 comprises a total of eight sleds. Via optical fabric412, each such sled may possess signaling connectivity with each of theseven other sleds in data center 400. For example, via optical fabric412, sled 404A-1 in rack 402A may possess signaling connectivity withsled 404A-2 in rack 402A, as well as the six other sleds 404B-1, 404B-2,404C-1, 404C-2, 404D-1, and 404D-2 that are distributed among the otherracks 402B, 402C, and 402D of data center 400. The embodiments are notlimited to this example.

FIG. 5 illustrates an overview of a connectivity scheme 500 that maygenerally be representative of link-layer connectivity that may beestablished in some embodiments among the various sleds of a datacenter, such as any of example data centers 100, 300, and 400 of FIGS.1, 3, and 4. Connectivity scheme 500 may be implemented using an opticalfabric that features a dual-mode optical switching infrastructure 514.Dual-mode optical switching infrastructure 514 may generally comprise aswitching infrastructure that is capable of receiving communicationsaccording to multiple link-layer protocols via a same unified set ofoptical signaling media, and properly switching such communications. Invarious embodiments, dual-mode optical switching infrastructure 514 maybe implemented using one or more dual-mode optical switches 515. Invarious embodiments, dual-mode optical switches 515 may generallycomprise high-radix switches. In some embodiments, dual-mode opticalswitches 515 may comprise multi-ply switches, such as four-ply switches.In various embodiments, dual-mode optical switches 515 may featureintegrated silicon photonics that enable them to switch communicationswith significantly reduced latency in comparison to conventionalswitching devices. In some embodiments, dual-mode optical switches 515may constitute leaf switches 530 in a leaf-spine architectureadditionally including one or more dual-mode optical spine switches 520.

In various embodiments, dual-mode optical switches may be capable ofreceiving both Ethernet protocol communications carrying InternetProtocol (IP packets) and communications according to a second,high-performance computing (HPC) link-layer protocol (e.g., Intel'sOmni-Path Architecture's, InfiniBand™) via optical signaling media of anoptical fabric. As reflected in FIG. 5, with respect to any particularpair of sleds 504A and 504B possessing optical signaling connectivity tothe optical fabric, connectivity scheme 500 may thus provide support forlink-layer connectivity via both Ethernet links and HPC links. Thus,both Ethernet and HPC communications can be supported by a singlehigh-bandwidth, low-latency switch fabric. The embodiments are notlimited to this example.

FIG. 6 illustrates a general overview of a rack architecture 600 thatmay be representative of an architecture of any particular one of theracks depicted in FIGS. 1 to 4 according to some embodiments. Asreflected in FIG. 6, rack architecture 600 may generally feature aplurality of sled spaces into which sleds may be inserted, each of whichmay be robotically-accessible via a rack access region 601. In theparticular non-limiting example depicted in FIG. 6, rack architecture600 features five sled spaces 603-1 to 603-5. Sled spaces 603-1 to 603-5feature respective multi-purpose connector modules (MPCMs) 616-1 to616-5.

FIG. 7 illustrates an example of a sled 704 that may be representativeof a sled of such a type. As shown in FIG. 7, sled 704 may comprise aset of physical resources 705, as well as an MPCM 716 designed to couplewith a counterpart MPCM when sled 704 is inserted into a sled space suchas any of sled spaces 603-1 to 603-5 of FIG. 6. Sled 704 may alsofeature an expansion connector 717. Expansion connector 717 maygenerally comprise a socket, slot, or other type of connection elementthat is capable of accepting one or more types of expansion modules,such as an expansion sled 718. By coupling with a counterpart connectoron expansion sled 718, expansion connector 717 may provide physicalresources 705 with access to supplemental computing resources 705Bresiding on expansion sled 718. The embodiments are not limited in thiscontext.

FIG. 8 illustrates an example of a rack architecture 800 that may berepresentative of a rack architecture that may be implemented in orderto provide support for sleds featuring expansion capabilities, such assled 704 of FIG. 7. In the particular non-limiting example depicted inFIG. 8, rack architecture 800 includes seven sled spaces 803-1 to 803-7,which feature respective MPCMs 816-1 to 816-7. Sled spaces 803-1 to803-7 include respective primary regions 803-1A to 803-7A and respectiveexpansion regions 803-1B to 803-7B. With respect to each such sledspace, when the corresponding MPCM is coupled with a counterpart MPCM ofan inserted sled, the primary region may generally constitute a regionof the sled space that physically accommodates the inserted sled. Theexpansion region may generally constitute a region of the sled spacethat can physically accommodate an expansion module, such as expansionsled 718 of FIG. 7, in the event that the inserted sled is configuredwith such a module.

FIG. 9 illustrates an example of a rack 902 that may be representativeof a rack implemented according to rack architecture 800 of FIG. 8according to some embodiments. In the particular non-limiting exampledepicted in FIG. 9, rack 902 features seven sled spaces 903-1 to 903-7,which include respective primary regions 903-1A to 903-7A and respectiveexpansion regions 903-1B to 903-7B. In various embodiments, temperaturecontrol in rack 902 may be implemented using an air cooling system. Forexample, as reflected in FIG. 9, rack 902 may feature a plurality offans 921 that are generally arranged to provide air cooling within thevarious sled spaces 903-1 to 903-7. In some embodiments, the height ofthe sled space is greater than the conventional “1U” server height. Insuch embodiments, fans 921 may generally comprise relatively slow, largediameter cooling fans as compared to fans used in conventional rackconfigurations. Running larger diameter cooling fans at lower speeds mayincrease fan lifetime relative to smaller diameter cooling fans runningat higher speeds while still providing the same amount of cooling. Thesleds are physically shallower than conventional rack dimensions.Further, components are arranged on each sled to reduce thermalshadowing (i.e., not arranged serially in the direction of air flow). Asa result, the wider, shallower sleds allow for an increase in deviceperformance because the devices can be operated at a higher thermalenvelope (e.g., 250 W) due to improved cooling (i.e., no thermalshadowing, more space between devices, more room for larger heat sinks,etc.).

MPCMs 916-1 to 916-7 may be configured to provide inserted sleds withaccess to power sourced by respective power modules 920-1 to 920-7, eachof which may draw power from an external power source 919. In variousembodiments, external power source 919 may deliver alternating current(AC) power to rack 902, and power modules 920-1 to 920-7 may beconfigured to convert such AC power to direct current (DC) power to besourced to inserted sleds. In some embodiments, for example, powermodules 920-1 to 920-7 may be configured to convert 277-volt AC powerinto 12-volt DC power for provision to inserted sleds via respectiveMPCMs 916-1 to 916-7. The embodiments are not limited to this example.

MPCMs 916-1 to 916-7 may also be arranged to provide inserted sleds withoptical signaling connectivity to a dual-mode optical switchinginfrastructure 914, which may be the same as—or similar to—dual-modeoptical switching infrastructure 514 of FIG. 5. In various embodiments,optical connectors contained in MPCMs 916-1 to 916-7 may be designed tocouple with counterpart optical connectors contained in MPCMs ofinserted sleds to provide such sleds with optical signaling connectivityto dual-mode optical switching infrastructure 914 via respective lengthsof optical cabling 922-1 to 922-7. In some embodiments, each such lengthof optical cabling may extend from its corresponding MPCM to an opticalinterconnect loom 923 that is external to the sled spaces of rack 902.In various embodiments, optical interconnect loom 923 may be arranged topass through a support post or other type of load-bearing element ofrack 902. The embodiments are not limited in this context. Becauseinserted sleds connect to an optical switching infrastructure via MPCMs,the resources typically spent in manually configuring the rack cablingto accommodate a newly inserted sled can be saved.

FIG. 10 illustrates an example of a sled 1004 that may be representativeof a sled designed for use in conjunction with rack 902 of FIG. 9according to some embodiments. Sled 1004 may feature an MPCM 1016 thatcomprises an optical connector 1016A and a power connector 1016B, andthat is designed to couple with a counterpart MPCM of a sled space inconjunction with insertion of MPCM 1016 into that sled space. CouplingMPCM 1016 with such a counterpart MPCM may cause power connector 1016 tocouple with a power connector comprised in the counterpart MPCM. Thismay generally enable physical resources 1005 of sled 1004 to sourcepower from an external source, via power connector 1016 and powertransmission media 1024 that conductively couples power connector 1016to physical resources 1005.

Sled 1004 may also include dual-mode optical network interface circuitry1026. Dual-mode optical network interface circuitry 1026 may generallycomprise circuitry that is capable of communicating over opticalsignaling media according to each of multiple link-layer protocolssupported by dual-mode optical switching infrastructure 914 of FIG. 9.In some embodiments, dual-mode optical network interface circuitry 1026may be capable both of Ethernet protocol communications and ofcommunications according to a second, high-performance protocol. Invarious embodiments, dual-mode optical network interface circuitry 1026may include one or more optical transceiver modules 1027, each of whichmay be capable of transmitting and receiving optical signals over eachof one or more optical channels. The embodiments are not limited in thiscontext.

Coupling MPCM 1016 with a counterpart MPCM of a sled space in a givenrack may cause optical connector 1016A to couple with an opticalconnector comprised in the counterpart MPCM. This may generallyestablish optical connectivity between optical cabling of the sled anddual-mode optical network interface circuitry 1026, via each of a set ofoptical channels 1025. Dual-mode optical network interface circuitry1026 may communicate with the physical resources 1005 of sled 1004 viaelectrical signaling media 1028. In addition to the dimensions of thesleds and arrangement of components on the sleds to provide improvedcooling and enable operation at a relatively higher thermal envelope(e.g., 250 W), as described above with reference to FIG. 9, in someembodiments, a sled may include one or more additional features tofacilitate air cooling, such as a heatpipe and/or heat sinks arranged todissipate heat generated by physical resources 1005. It is worthy ofnote that although the example sled 1004 depicted in FIG. 10 does notfeature an expansion connector, any given sled that features the designelements of sled 1004 may also feature an expansion connector accordingto some embodiments. The embodiments are not limited in this context.

FIG. 11 illustrates an example of a data center 1100 that may generallybe representative of one in/for which one or more techniques describedherein may be implemented according to various embodiments. As reflectedin FIG. 11, a physical infrastructure management framework 1150A may beimplemented to facilitate management of a physical infrastructure 1100Aof data center 1100. In various embodiments, one function of physicalinfrastructure management framework 1150A may be to manage automatedmaintenance functions within data center 1100, such as the use ofrobotic maintenance equipment to service computing equipment withinphysical infrastructure 1100A. In some embodiments, physicalinfrastructure 1100A may feature an advanced telemetry system thatperforms telemetry reporting that is sufficiently robust to supportremote automated management of physical infrastructure 1100A. In variousembodiments, telemetry information provided by such an advancedtelemetry system may support features such as failureprediction/prevention capabilities and capacity planning capabilities.In some embodiments, physical infrastructure management framework 1150Amay also be configured to manage authentication of physicalinfrastructure components using hardware attestation techniques. Forexample, robots may verify the authenticity of components beforeinstallation by analyzing information collected from a radio frequencyidentification (RFID) tag associated with each component to beinstalled. The embodiments are not limited in this context.

As shown in FIG. 11, the physical infrastructure 1100A of data center1100 may comprise an optical fabric 1112, which may include a dual-modeoptical switching infrastructure 1114. Optical fabric 1112 and dual-modeoptical switching infrastructure 1114 may be the same as—or similarto—optical fabric 412 of FIG. 4 and dual-mode optical switchinginfrastructure 514 of FIG. 5, respectively, and may providehigh-bandwidth, low-latency, multi-protocol connectivity among sleds ofdata center 1100. As discussed above, with reference to FIG. 1, invarious embodiments, the availability of such connectivity may make itfeasible to disaggregate and dynamically pool resources such asaccelerators, memory, and storage. In some embodiments, for example, oneor more pooled accelerator sleds 1130 may be included among the physicalinfrastructure 1100A of data center 1100, each of which may comprise apool of accelerator resources—such as co-processors and/or FPGAs, forexample—that is globally accessible to other sleds via optical fabric1112 and dual-mode optical switching infrastructure 1114.

In another example, in various embodiments, one or more pooled storagesleds 1132 may be included among the physical infrastructure 1100A ofdata center 1100, each of which may comprise a pool of storage resourcesthat is globally accessible to other sleds via optical fabric 1112 anddual-mode optical switching infrastructure 1114. In some embodiments,such pooled storage sleds 1132 may comprise pools of solid-state storagedevices such as solid-state drives (SSDs). In various embodiments, oneor more high-performance processing sleds 1134 may be included among thephysical infrastructure 1100A of data center 1100. In some embodiments,high-performance processing sleds 1134 may comprise pools ofhigh-performance processors, as well as cooling features that enhanceair cooling to yield a higher thermal envelope of up to 250 W or more.In various embodiments, any given high-performance processing sled 1134may feature an expansion connector 1117 that can accept a far memoryexpansion sled, such that the far memory that is locally available tothat high-performance processing sled 1134 is disaggregated from theprocessors and near memory comprised on that sled. In some embodiments,such a high-performance processing sled 1134 may be configured with farmemory using an expansion sled that comprises low-latency SSD storage.The optical infrastructure allows for compute resources on one sled toutilize remote accelerator/FPGA, memory, and/or SSD resources that aredisaggregated on a sled located on the same rack or any other rack inthe data center. The remote resources can be located one switch jumpaway or two-switch jumps away in the spine-leaf network architecturedescribed above with reference to FIG. 5. The embodiments are notlimited in this context.

In various embodiments, one or more layers of abstraction may be appliedto the physical resources of physical infrastructure 1100A in order todefine a virtual infrastructure, such as a software-definedinfrastructure 1100B. In some embodiments, virtual computing resources1136 of software-defined infrastructure 1100B may be allocated tosupport the provision of cloud services 1140. In various embodiments,particular sets of virtual computing resources 1136 may be grouped forprovision to cloud services 1140 in the form of software-definedinfrastructure (SDI) services 1138. Examples of cloud services 1140 mayinclude—without limitation—software as a service (SaaS) services 1142,platform as a service (PaaS) services 1144, and infrastructure as aservice (IaaS) services 1146.

In some embodiments, management of software-defined infrastructure 1100Bmay be conducted using a virtual infrastructure management framework1150B. In various embodiments, virtual infrastructure managementframework 1150B may be designed to implement workload fingerprintingtechniques and/or machine-learning techniques in conjunction withmanaging allocation of virtual computing resources 1136 and/or SDIservices 1138 to cloud services 1140. In some embodiments, virtualinfrastructure management framework 1150B may use/consult telemetry datain conjunction with performing such resource allocation. In variousembodiments, an application/service management framework 1150C may beimplemented in order to provide QoS management capabilities for cloudservices 1140. The embodiments are not limited in this context.

Referring now to FIG. 12, an illustrative system 1200 for determiningset membership, which may be implemented in accordance with the datacenters 100, 300, 400, 1100 described above with reference to FIGS. 1,3, 4, and 11, is shown. The illustrative system 1200 includes a computedevice 1202 that includes an accelerator 1204, a memory 1206, one ormore processors 1208, and one or more storage devices 1210. In use, asdescribed further below, the accelerator 1204 may filter a databasecolumn to determine a set of elements from the database column thatsatisfy a set membership query condition requested by a processor 1208.To do so, the accelerator 1204 may generate a definition table thatincludes a set membership definition table, which is a bit vectorincluding multiple one-bit entries indicating element values in the setmembership that satisfy the set membership query condition. In otherwords, the set membership definition table includes one or morepredicate bits indicative of set membership. In the illustrativeembodiment, the accelerator 1240 may store the set membership bit vectoron a different type of definition tables on the accelerator 1240 basedon a size or width of each element of the input database column. Forexample, if the width of each database column element is less than 8bits, the set membership bit vector may be stored in a small definitiontable with multiple read ports (e.g., multiplexors) to provide multiplereads per cycle. Alternatively, if the width of the database columnelement is greater than 8 bits, the set membership bit vector may bestored in a large definition table. The accelerator 1204 may configurethe large definition table to store duplicate copies of the setmembership bit vector to support parallel accesses. Subsequently, theaccelerator 1204 may receive input data, which is a packed array ofunsigned integers of column data from the database with a given elementwidth, to determine a set of elements of the input data that satisfiesthe set membership query condition by looking up the element values inthe set membership bit vector. To do so, the accelerator 1204 may adjusta width of the elements of the input data by pre-processing the packedunsigned integers of column data in order to support set membershipqueries on any bit-width of elements of the database based on a datapath width of the accelerator 1240. For example, the pre-processing ofthe input data may include aligning the elements of the input data ortruncating high and/or low bits to adjust the element width of the inputdata to a fixed width. The pre-processing of the input data may alsoensure that a largest number of elements are processed in each cycle.Subsequently, the accelerator 1240 may generate an output indicative ofa set of elements that satisfies the set membership query condition andtransfer the output to the memory 1206 of the compute device 1202 forfurther analysis or processing by one or more processors 1208. Byperforming the set membership queries on the hardware accelerator 1204instead of the processor 1208, the system 1200 may increase performanceand power efficiency by avoiding moving a large amount of data to theprocessor(s) 1208 for the set membership queries.

For example, the database stored in the memory 1206 of the computedevice 1202 may include a table with a list of names of people, theirresidency information, and their income. The processor 1208 requests theaccelerator 1204 to filter the database to list only those people wholive in New England (i.e., ME, VT, NH, MA, RI, CT). In response, theaccelerator 1204 generates a definition table with a set membership bitvector that defines element values that satisfy the set membership querycondition (i.e., ME, VT, NH, MA, RI, CT). In this example, the setmembership bit vector may include six predicate bits that each have avalue of 1, each of which corresponds to one of New England states. Theremaining bits of the set membership bit vector may each have a value of0, indicating states that are not in New England. Subsequently, theaccelerator 1204 receives the residency information column data from thememory 1206 and determines a set of elements corresponding to people wholive in New England by looking up the element value of the residencycolumn data for each person in the set membership bit vector. Theaccelerator 1204 then generates an output which indicates columnelements of the database that match the set membership query condition,where each index of the output corresponds to a row in the database andthus corresponds to a person.

The accelerator 1204 may be embodied as any coprocessor,application-specific integrated circuit (ASIC), field-programmable gatearray (FPGA), a system-on-a-chip (SOC), an application specificintegrated circuit (ASIC), functional block, IP core, or other hardwareaccelerator of the compute device 1202 capable of performing thefunctions described herein. As discussed above, the accelerator 1204 isconfigured to determine a set of elements from the database thatsatisfies a set membership query condition requested by the processor(s)1208. To do so, as shown in FIG. 12, the accelerator 1204 includes adecompressor 1212, an input pre-processing unit 1214, a lookup requestgenerator unit 1216, and an output processing unit 1218. As discussedabove, the accelerator 1204 also includes a definition table 1220 thatmay be stored in external memory 1222 of the accelerator 1204 and localmemory 1224 of the accelerator 1204.

The decompressor 1212 may be embodied as any hardware component(s) orcircuitry capable of decompressing the input data. Typically, the inputdata is compressed column data stored in the memory 1206. As such, thedecompressor 1212 may determine whether the input data is compresseddata and decompress the compressed input data in response to determiningthat the input data is compressed.

The input pre-processing unit 1214 may be embodied as any hardwarecomponent(s) or circuitry capable of pre-processing the input data tosupport set membership queries on any bit-width of elements of thedatabase. To do so, the input pre-processing unit 1214 may determine alargest power of 2 elements (i.e., 2^(n) elements) that is to beprocessed in each cycle as a function of an element width of the inputdata and a data path width of the accelerator 1204. The inputpre-processing unit 1214 may align the elements of the uncompressedinput data (e.g., the packed array of unsigned integers of column data)and prepend zero to each element of the input data based on the datapath width in order to process the largest power of 2 elements percycle. For example, if the accelerator 1204 has a 32 bit wide data path,the input pre-processing unit 1214 may process 32 elements for anelement width of 1 bit, 16 elements for an element width of 2 bits, 8elements for element widths 3 or 4 bits, 4 elements for element widthsfrom 5 to 8 bits, and so on.

The lookup request generator unit 1216 may be embodied as any hardwarecomponent(s) or circuitry capable of generating a lookup request foreach element of the input data to determine whether that elementsatisfies the set membership query condition. To do so, the lookuprequest generator unit 1216 may generate a read request address for thecorresponding element to access the definition table. Since the inputdata is pre-processed, the lookup request generator unit 1216 mayextract each element and use the corresponding element value as a readrequest address to issue a read request to the corresponding definitiontable.

The output processing unit 1218 may be embodied as any hardwarecomponent(s) or circuitry capable of generating an output that indicatesall elements that match the set membership query condition. To do so,the output processing unit 1218 may be configured to extract a bit foreach element that indicates whether the corresponding element matchesthe set membership query condition. The output processing unit 1218 maybe further configured to accumulate the extracted bits until a width ofthe output reaches the data path width to transmit the output to thememory 1206 for further analysis by one or more processors 1208. In someembodiments, the output processing unit 1218 may directly communicatewith one or more processors 1208 to transmit the output.

The processor 1208 may be embodied as any type of processor capable ofperforming the functions described herein. For example, the processor1208 may be embodied as a single or multi-core processor(s), digitalsignal processor, microcontroller, or other processor orprocessing/controlling circuit. Similarly, the memory 1206 may beembodied as any type of volatile or non-volatile memory or data storagecapable of performing the functions described herein. In operation, thememory 1206 may store various data and software used during operation ofthe compute device 1202 such operating systems, applications, programs,libraries, and drivers. The memory 1206 is communicatively coupled tothe processor 1208 via the input/output (I/O) subsystem (not shown),which may be embodied as circuitry and/or components to facilitateinput/output operations with the processor 1208, the accelerator 1204,the memory 1206, the one or more storage devices 1210, and othercomponents of the compute device 1202. For example, the I/O subsystemmay be embodied as, or otherwise include, memory controller hubs,input/output control hubs, sensor hubs, firmware devices, communicationlinks (i.e., point-to-point links, bus links, wires, cables, lightguides, printed circuit board traces, etc.) and/or other components andsubsystems to facilitate the input/output operations. In someembodiments, the I/O subsystem may form a portion of a system-on-a-chip(SoC) and be incorporated, along with the processor 1208, the memory1206, and other components of the compute device 1202, on a singleintegrated circuit chip.

The memory 1206 may be embodied as any type of volatile (e.g., dynamicrandom access memory (DRAM), etc.) or non-volatile memory or datastorage capable of performing the functions described herein. Volatilememory may be a storage medium that requires power to maintain the stateof data stored by the medium. Non-limiting examples of volatile memorymay include various types of random access memory (RAM), such as dynamicrandom access memory (DRAM) or static random access memory (SRAM). Oneparticular type of DRAM that may be used in a memory module issynchronous dynamic random access memory (SDRAM). In particularembodiments, DRAM of a memory component may comply with a standardpromulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 forLow Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, andJESD209-4 for LPDDR4 (these standards are available at www.jedec.org).Such standards (and similar standards) may be referred to as DDR-basedstandards and communication interfaces of the storage devices thatimplement such standards may be referred to as DDR-based interfaces.

In one embodiment, the memory device is a block addressable memorydevice, such as those based on NAND or NOR technologies. A memory devicemay also include future generation nonvolatile devices, such as a threedimensional crosspoint memory device (e.g., Intel 3D XPoint™ memory), orother byte addressable write-in-place nonvolatile memory devices. In oneembodiment, the memory device may be or may include memory devices thatuse chalcogenide glass, multi-threshold level NAND flash memory, NORflash memory, single or multi-level Phase Change Memory (PCM), aresistive memory, nanowire memory, ferroelectric transistor randomaccess memory (FeTRAM), anti-ferroelectric memory, magnetoresistiverandom access memory (MRAM) memory that incorporates memristortechnology, resistive memory including the metal oxide base, the oxygenvacancy base and the conductive bridge Random Access Memory (CB-RAM), orspin transfer torque (STT)-MRAM, a spintronic magnetic junction memorybased device, a magnetic tunneling junction (MTJ) based device, a DW(Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristorbased memory device, or a combination of any of the above, or othermemory. The memory device may refer to the die itself and/or to apackaged memory product.

In some embodiments, 3D crosspoint memory (e.g., Intel 3D XPoint™memory) may comprise a transistor-less stackable cross pointarchitecture in which memory cells sit at the intersection of word linesand bit lines and are individually addressable and in which bit storageis based on a change in bulk resistance. In some embodiments, all or aportion of the memory 1206 may be integrated into the processor 1208. Inoperation, the memory 1206 may store various software and data usedduring operation such as resource utilization data, resourceavailability data, application programming interface (API) data,applications, programs, and libraries.

The illustrative storage devices 1210 may be embodied as any type ofdevices configured for short-term or long-term storage of data such as,for example, memory devices and circuits, memory cards, hard diskdrives, solid-state drives, or other data storage devices. Each storagedevice 1210 may include a system partition that stores data and firmwarecode for the storage device 1210. Each storage device 1210 may alsoinclude one or more operating system partitions that store data filesand executables for operating systems.

Although illustrated in FIG. 12 as a single compute device 1202, itshould be understood that in some embodiments the functions of thecompute device 1202 may be performed by one or more sleds in a datacenter. In such embodiments, the accelerator 1204 may be embodied as oneor more accelerator sled 204-2 (e.g., physical accelerator resources205-2), the memory 1206 may be embodied as one or more memory sled 204-3(e.g., physical memory resources 205-3), one or more processors 1208 maybe embodied as one or more compute sled 204-4 (e.g., physical computeresources 205-4), one or more storage devices 1210 may be embodied asone or more storage sleds 204-1 (e.g., physical storage resources205-1).

Referring now to FIG. 13, in the illustrative embodiment, theaccelerator 1204 of the compute device 1202 may establish an environment1300 during operation. In the illustrative embodiment, the environment1300 includes a large bit vector definition table 1340 and a small bitvector definition table 1350. The large bit vector definition table 1340may be embodied as any data indicative of a set membership bit vectorfor elements that have a bit-width greater than a predefined number ofbit-width. Whereas, the small bit vector definition table 1350 may beembodied as any data indicative of a set membership bit vector forelements that have a bit-width smaller than the predefined number ofbit-width. As discussed above, the set membership bit vector is aplurality of one-bit entries indicating element values in the setmembership that satisfy the set membership query condition.Additionally, the illustrative environment 1300 includes an input/output(I/O) communicator 1310, a decompressor 1320, and complex filter 1330.The complex filter 1330 further includes a definition table generator1332, an input data pre-processor 1334, a search request generator 1336,and an output generator 1338. Each of the components of the environment1300 may be embodied as hardware, firmware, software, or a combinationthereof. As such, in some embodiments, one or more of the components ofthe environment 1300 may be embodied as circuitry or a collection ofelectrical devices (e.g., I/O communicator circuitry 1310, decompressorcircuitry 1320, complex filter circuitry 1330, definition tablegenerator circuitry 1332, input data pre-processor circuitry 1334,search request generator circuitry 1336, output generator circuitry1338, etc.).

In the illustrative environment 1300, the I/O communicator 1310 isconfigured to facilitate inbound and outbound network communications(e.g., network traffic, network packets, network flows, etc.) to andfrom the accelerator 1204, respectively. To do so, the I/O communicator1310 is configured to receive and process data from the memory 1206based on one or more set membership queries received from a processor1208 of the compute device 1202. The I/O communicator 1310 is furtherconfigured to transmit an output to the memory 1206. In someembodiments, the accelerator 1204 may receive from or transmit to one ormore storage devices 1210. Accordingly, in some embodiments, at least aportion of the functionality of the I/O communicator 1310 may beperformed by communication circuitry of the compute device 1202.

The decompressor 1320, which may be embodied as hardware, firmware,software, virtualized hardware, emulated architecture, and/or acombination thereof as discussed above, is configured to decompress theinput data. The decompressor 1212 is configured to determine whether theinput data is compressed data and decompress the compressed input datain response to determining that the input data is compressed.

The complex filter 1330, which may be embodied as hardware, firmware,software, virtualized hardware, emulated architecture, and/or acombination thereof as discussed above, is configured to filter theinput data to determine a set of elements from database that satisfies aset membership query condition requested by a processor 1208. To do so,the complex filter 1330 includes the definition table generator 1332,the input data pre-processor 1334, the search request generator 1336,and the output generator 1338.

The definition table generator 1332 is configured to generate adefinition table. To do so, the definition table generator 1332 isconfigured to generate a set membership bit vector. As described above,the set membership bit vector is a plurality of one-bit entriesindicating element values in the set membership that satisfy the setmembership query condition. In the illustrative embodiment, thedefinition table generator 1332 is configured to construct a differenttype of definition table (e.g., a small or large definition table) onthe accelerator 1240 based on the width of the each column element tostore the set membership bit vector. If the definition table generator1332 determines that the width of each column element is less than apredefined width, the definition table generator 1332 constructs a smalldefinition table that has many read ports as necessary to satisfy atarget throughput based on the width of the data path of the accelerator1204. For example, if the width of column elements that satisfy the setmembership query condition is less than 8 bits, the set membership bitvector is stored in a small definition table with multiple read ports toprovide multiple reads per cycle. To generate a definition table thatsupports elements up to 8 bits, the definition table generator 1332implements 256 flip flops to construct a small definition table. In thisexample, if the width of the data path of the accelerator 1204 is 32bit, the definition table generator 1332 constructs the small definitiontable with 2 flip flops for 32 read ports of a 1 bit element (e.g., 2:1multiplexers), 4 flip flops for 16 read ports of a 2 bit element (e.g.,4:1 multiplexers), 16 flip flops for 8 read ports of a 3 or 4 bitelement (e.g., 16:1 multiplexers), and remaining flip flops for 4 readports. Alternatively, if the width of column elements is greater than 8bits, the set membership bit vector is stored in a large definitiontable. The accelerator 1204 may configure the large definition table tostore duplicate copies of the set membership bit vector to supportparallel accesses. It should be appreciated that, in some embodiments,the accelerator 1204 may also configure the small bit-map output tableto store multiple copies of the set membership bit vector to supportmultiple accesses.

The input data pre-processor 1334 is configured to pre-process the inputdata to support set membership queries on any bit-width of elements ofthe database. To do so, the input data pre-processor 1334 is configuredto determine a largest power of 2 elements (i.e., 2^(n) elements) thatis to be processed in each cycle as a function of an element width ofthe input data and a data path width of the accelerator 1204. The inputdata pre-processor 1334 is further configured to align the elements ofthe uncompressed input data (i.e., the packed array of unsigned integersof column data) and prepend zero to each element of the input data basedon the data path width in order to process the largest power of 2elements per cycle. For example, if the accelerator 1204 has a 32 bitwide data path, the input data pre-processor 1334 may process 32elements for element with 1 bit, 16 elements for element width of 2bits, 8 elements for element widths 3 or 4 bits, or 4 elements forelement widths from 5 to 8 bits, and so on.

The search request generator 1336 is configured to generate a lookuprequest for each element of the input data to determine whether thatelement satisfies the set membership query condition. To do so, thesearch request generator 1336 may generate a read request address forthe corresponding element to access the definition table. Since theinput data is pre-processed, the search request generator 1336 mayextract each element and use the corresponding element value as a readrequest address to issue a read request to the corresponding definitiontable.

The output generator 1338 is configured to generate an output thatindicates all elements that match the set membership query condition. Todo so, in some embodiments, the output generator 1338 may be configuredto extract a bit for each element that indicates whether thecorresponding element matches the set membership query condition. Theoutput generator 1338 may be further configured to accumulate theextracted bits until a width of the output reaches the data path widthand transmit the output to the memory 1206 for further processing by oneor more processors 1208. In some embodiments, the output generator 1338may directly communicate with one or more processors 1208 to transmitthe output.

Referring now to FIGS. 14 and 15, in use, the accelerator 1204 of thecompute device 1202 may execute a method 1400 for determining setmembership. The method 1400 begins with block 1402, in which theaccelerator 1204 imports input data from the memory 1206 of the computedevice 1202. Typically, the input data is compressed data stored in thememory 1206. As such, the accelerator 1204 decompresses the compressedinput data as indicated in block 1404.

In block 1406, the accelerator 1204 receives definition tableconfiguration data from a requesting processor 1208 of the computedevice 1202. For example, the accelerator 1204 may receive from theprocessor 1208 a pointer to definition table configuration data in thememory 1206. However, it should be appreciated that, in someembodiments, the definition table configuration data may be receivedfrom other components of the compute device 1202. As described above,the definition table configuration data includes a set membership querycondition that is to be used to filter the input data. Accordingly, theaccelerator 1204 determines a set membership query condition based onthe definition table configuration data as indicated in block 1408.Additionally, the accelerator 1204 further determines an element widthof the input data as indicated in block 1410 and a number of elements tobe processed per cycle based on the element width and a data path widthof the accelerator 1204 as indicated in block 1412.

In block 1414, the accelerator 1204 generates a set membership bitvector based on the definition table configuration data. To do so, theaccelerator 1204 generates the set membership bit vector that includes aplurality of one-bit entries indicating all element values that satisfythe set membership query condition as indicated in block 1416.Accordingly, the set membership bit vector has a size equal to two tothe element width power. For example, the membership bit vector for8-bit elements includes 2⁸ or 256 bits, the membership bit vector for32-bit elements includes 2³² bits or 512 MB, and so on.

Subsequently, the accelerator 1204 constructs a definition table tostore the set membership bit vector. As described above, the accelerator1240 configures a different definition table on the accelerator 1240based on a width of the element. To do so, in block 1418, theaccelerator 1204 determines whether the element width is greater than apredefined width. If the accelerator 1204 determines that the elementwidth is smaller than the predefined threshold of element width, themethod 1400 advances to block 1420. In block 1420, the accelerator 1204constructs a small definition table to store the set membership bitvector. The small definition table is to support multiple read ports toprovide multiple reads per cycle as indicated in block 1422. Forexample, if the element width is less than 8 bits, the set membershipbit vector is stored in a small definition table with multiple readports to provide multiple reads per cycle.

Alternatively, if the accelerator 1204 determines that the element widthis greater than the predefined threshold of element width in block 1418,the method 1400 advances to block 1424. In block 1424, the accelerator1204 constructs a large definition table to store the set membership bitvector. Although multiple read ports may be implemented to construct asmall definition table for processing data having a small element width,implementing multiple read ports for a large data having a large elementwidth may be impractical and costly. As such, the accelerator 1204 maystore duplicate copies of the set membership bit vector to supportparallel accesses per cycle as indicated in block 1426. To do so, themembership bit vectors are stored in different banks such that eachmembership bit vector in each bank is accessed simultaneously, therebysupporting parallel accesses. For example, if the width of each elementis greater than 8 bits, the accelerator 1204 may configure a largedefinition table to store duplicate copies of the set membership bitvector to support parallel accesses. It should be appreciated that, insome embodiments, the accelerator 1204 may construct the definitiontable prior to generating the set membership bit vector.

Subsequently, in block 1428 shown in FIG. 15, the accelerator 1204pre-processes the input data to prepare the elements of the input datafor the set membership function. To do so, the accelerator 1204 mayalign the elements of the input data (i.e., the packed unsigned integersof column data) based on the number of elements that is to be processedin each cycle as indicated block 1430. As described above, the number ofelements that is to be processed in each cycle is determined based onthe element width of the input data and a data path width of theaccelerator 1204. Additionally, the accelerator 1204 prepends zeros toeach element of the input data based on the data path width in order toprocess a largest power of 2 elements per cycle (i.e., largest 2^(n)elements/cycle). For example, if the accelerator 1204 has a 32 bit widedata path, the accelerator 1204 may process 32 elements for element with1 bit, 16 elements for element width of 2 bits, 8 elements for elementwidths 3 or 4 bits, or 4 elements for element widths from 5 to 8 bits,and so on.

In block 1434, the accelerator 1204 generates a lookup request for eachelement of the input data to determine whether that element satisfiesthe set membership query condition. To do so, the accelerator 1204 maygenerate a read request address for the corresponding element to accessthe definition table as indicated in block 1436. Since the input data ispre-processed and aligned with the definition table, the accelerator1204 may extract each element and use the corresponding element value asa read request address to issue a read request to the correspondingdefinition table. In block 1438, the lookup request is transmitted tothe corresponding definition table.

Subsequently, in block 1440, the accelerator 1204 accesses thecorresponding definition table to determine whether the elementsatisfies the set membership query condition by evaluating the readrequest address to the set membership bit vector stored in thedefinition table. For example, the element may be determined to satisfythe set membership query condition if the element value matches at leastone predicate bit.

As a result, in block 1442, the accelerator 1204 generates an outputthat indicates element(s) that matches the set membership querycondition. To do so, in block 1444, the accelerator 1204 may extract abit for each element that indicates whether the corresponding elementmatches the set membership query condition as indicated in block 1452.In some embodiments, in block 1446, the accelerator 1204 may accumulatethe extracted bits until a width of the output reaches the data pathwidth of the accelerator and transmit the output to the memory 1206 forfurther processing by one or more processors 1208. In some embodiments,the output may be directly transmitted to the processor 1208.

EXAMPLES

Illustrative examples of the technologies disclosed herein are providedbelow. An embodiment of the technologies may include any one or more,and any combination of, the examples described below.

Example 1 includes a computing device for determining set membership,the computing device comprising one or more accelerator devices, eachaccelerator device is to receive input data and definition tableconfiguration data, the input data including a packed array of unsignedintegers of column data from database and the definition tableconfiguration data including a set membership query condition; generate,in response to receiving the definition table configuration data, adefinition table indicative of element values that satisfy the setmembership query condition; generate a lookup request for an element ofthe column data of the input data; perform the lookup request byaccessing the definition table to determine whether the elementsatisfies the set membership query condition; and generate an outputindicative of whether the element is a member of the set membership.

Example 2 includes the subject matter of Example 1, and wherein the eachaccelerator device is further to determine a number of elements to beprocessed in each cycle based on based on an element width of the inputdata and a data path width of the accelerator device.

Example 3 includes the subject matter of any of Examples 1 and 2, andwherein the each accelerator device is further to decompress, inresponse to receiving the input data, the input data; and pre-process,in response to decompressing the input data, the decompressed inputdata.

Example 4 includes the subject matter of any of Examples 1-3, andwherein to pre-process the decompressed input data comprises to alignelements of the column data of the input data based on a width ofelements of the decompressed input data and to prepend zeroes to match adata path width.

Example 5 includes the subject matter of any of Examples 1-4, andwherein to generate the definition table comprises to generate a setmembership bit vector with one or more predicate bits indicative of setmembership.

Example 6 includes the subject matter of any of Examples 1-5, andwherein to generate the definition table comprises to determine whethera width of each element in the input data exceeds a threshold;construct, in response to a determination that the width of elementsexceeds the threshold, a large definition table to store the setmembership bit vector; and construct, in response to a determinationthat the width of elements does not exceed the threshold, a smalldefinition table to store the set membership bit vector.

Example 7 includes the subject matter of any of Examples 1-6, andwherein the definition table supports parallel accesses by duplicatingthe definition table.

Example 8 includes the subject matter of any of Examples 1-7, andwherein the definition table supports parallel accesses by implementingmultiple read ports.

Example 9 includes the subject matter of any of Examples 1-8, andwherein to perform the lookup request comprises to perform the lookuprequest by accessing the definition table to determine whether theelement matches at least one predicate bit of the set membership bitvector.

Example 10 includes the subject matter of any of Examples 1-9, andwherein to perform the lookup request comprises to determine whether awidth of the element exceeds a threshold; access, in response to adetermination that the width of the element exceeds the threshold, thelarge definition table to determine whether the element satisfies theset membership query condition; and access, in response to adetermination that the width of the element does not exceed thethreshold, the small definition table to determine whether the elementsatisfies the set membership query condition.

Example 11 includes the subject matter of any of Examples 1-10, andwherein to generate the output indicative of whether the elementsatisfied the set membership query condition comprises to extract aone-bit value indicating whether the element satisfies the setmembership query condition.

Example 12 includes the subject matter of any of Examples 1-11, andwherein to generate the output indicative of whether the elementsatisfied the set membership query condition comprises to pack extractedone-bit values until a width of the extracted one-bit values matches adata path width.

Example 13 includes a method for determining set membership by acomputing device, the method comprising receiving, by an accelerator ofthe computing device, input data and definition table configurationdata, the input data including a packed array of unsigned integers ofcolumn data from database and the definition table configuration dataincluding a set membership query condition; generating, in response toreceiving the definition table configuration data and by theaccelerator, a definition table indicative of element values thatsatisfy the set membership query condition; generating, by theaccelerator, a lookup request for an element of the column data of theinput data; performing, by the accelerator, the lookup request byaccessing the definition table to determine whether the elementsatisfies the set membership query condition; and generating, by theaccelerator, an output indicative of whether the element is a member ofthe set membership.

Example 14 includes the subject matter of Example 13, and furtherincluding, determining in response to receiving the definition tableconfiguration data and by the accelerator, a number of elements to beprocessed in each cycle based on based on an element width of the inputdata and a data path width of the accelerator device.

Example 15 includes the subject matter of any of Examples 13 and 14, andfurther including decompressing, by the accelerator and in response toimporting the input data, the input data; and pre-processing, by theaccelerator and in response to decompressing the input data, thedecompressed input data.

Example 16 includes the subject matter of any of Examples 13-15, andwherein pre-processing the decompressed input data comprises aligning,by the accelerator, elements of the column data of the input data basedon a width of elements of the decompressed input data and prepending, bythe accelerator, zeroes to match a data path width.

Example 17 includes the subject matter of any of Examples 13-16, andwherein generating the definition table comprises generating, by theaccelerator, a set membership bit vector with one or more predicate bitsindicative of set membership.

Example 18 includes the subject matter of any of Examples 13-17, andwherein generating the definition table based on the definition tableconfiguration data comprises determining, by the accelerator, whether awidth of each element in the input data exceeds a threshold;constructing, in response to a determination that the width of elementsexceeds the threshold, a large definition table to store the setmembership bit vector; and constructing, in response to a determinationthat the width of elements does not exceed the threshold, a smalldefinition table to store the set membership bit vector.

Example 19 includes the subject matter of any of Examples 13-18, andwherein the definition table supports parallel accesses by duplicatingthe definition table.

Example 20 includes the subject matter of any of Examples 13-19, andwherein the definition table supports parallel accesses by implementingmultiple read ports.

Example 21 includes the subject matter of any of Examples 13-20, andwherein performing the lookup request comprises performing, by theaccelerator, the lookup request by accessing the definition table todetermine whether the element matches at least one predicate bit of theset membership bit vector.

Example 22 includes the subject matter of any of Examples 13-21, andwherein performing the lookup request by accessing the definition tableto determine whether the element satisfies the set membership querycondition comprises determining, by the accelerator, whether a width ofthe element exceeds a threshold; accessing, in response to adetermination that the width of the element exceeds the threshold and bythe accelerator, the large definition table to determine whether theelement satisfies the set membership query condition; and accessing, inresponse to a determination that the width of the element does notexceed the threshold and by the accelerator, the small definition tableto determine whether the element satisfies the set membership querycondition.

Example 23 includes the subject matter of any of Examples 13-22, andwherein generating the output indicative of whether the elementsatisfied the set membership query condition comprises extracting aone-bit value indicating whether the element satisfies the setmembership query condition.

Example 24 includes the subject matter of any of Examples 13-23, andwherein generating the output indicative of whether the elementsatisfied the set membership query condition comprises packing extractedone-bit values until a width of the extracted one-bit values matches adata path width.

Example 25 includes a compute device comprising means for performing themethod of any of Examples 13-24.

Example 26 includes one or more machine-readable storage mediacomprising a plurality of instructions stored thereon that, in responseto being executed, cause a compute device to perform the method of anyof Examples 13-24.

Example 27 includes a compute device comprising a compute engine toperform the method of any of Examples 13-24.

Example 28 includes a computing device for determining set membership,the computing device comprising one or more accelerator devices, eachaccelerator device comprising means for receiving input data anddefinition table configuration data, the input data including a packedarray of unsigned integers of column data from database and thedefinition table configuration data including a set membership querycondition; means for generating, in response to receiving the definitiontable configuration data, a definition table indicative of elementvalues that satisfy the set membership query condition; means forgenerating a lookup request for an element of the column data of theinput data; means for performing the lookup request by accessing thedefinition table to determine whether the element satisfies the setmembership query condition; and means for generating an outputindicative of whether the element is a member of the set membership.

Example 29 includes the subject matter of Example 28, and wherein theaccelerator device further comprising means for determining, in responseto receiving the definition table configuration data and by theaccelerator, a number of elements to be processed in each cycle based onbased on an element width of the input data and a data path width of theaccelerator device.

Example 30 includes the subject matter of any of Examples 28 and 29, andwherein the accelerator device further comprising means fordecompressing, in response to importing the input data, the input data;and means for pre-processing, in response to decompressing the inputdata, the decompressed input data.

Example 31 includes the subject matter of any of Examples 28-30, andwherein the means for pre-processing the decompressed input datacomprises means for aligning elements of the column data of the inputdata based on a width of elements of the decompressed input data andmeans for prepending zeroes to match a data path width.

Example 32 includes the subject matter of any of Examples 28-31, andwherein the means for generating the definition table comprises meansfor generating a set membership bit vector with one or more predicatebits indicative of set membership.

Example 33 includes the subject matter of any of Examples 28-32, andwherein the means for generating the definition table based on thedefinition table configuration data comprises means for determiningwhether a width of each element in the input data exceeds a threshold;means for constructing, in response to a determination that the width ofelements exceeds the threshold, a large definition table to store theset membership bit vector; and means for constructing, in response to adetermination that the width of elements does not exceed the threshold,a small definition table to store the set membership bit vector.

Example 34 includes the subject matter of any of Examples 28-33, andwherein the definition table supports parallel accesses by duplicatingthe definition table.

Example 35 includes the subject matter of any of Examples 28-34, andwherein the definition table supports parallel accesses by implementingmultiple read ports.

Example 36 includes the subject matter of any of Examples 28-35, andwherein the means for performing the lookup request comprises means forperforming the lookup request by accessing the definition table todetermine whether the element matches at least one predicate bit of theset membership bit vector.

Example 37 includes the subject matter of any of Examples 28-36, andwherein the means for performing the lookup request by accessing thedefinition table to determine whether the element satisfies the setmembership query condition comprises means for determining whether awidth of the element exceeds a threshold; means for accessing, inresponse to a determination that the width of the element exceeds thethreshold, the large definition table to determine whether the elementsatisfies the set membership query condition; and means for accessing,in response to a determination that the width of the element does notexceed the threshold, the small definition table to determine whetherthe element satisfies the set membership query condition.

Example 38 includes the subject matter of any of Examples 28-37, andwherein the means for generating the output indicative of whether theelement satisfied the set membership query condition comprises means forextracting a one-bit value indicating whether the element satisfies theset membership query condition and packing extracted one-bit valuesuntil a width of the extracted one-bit values matches a data path width.

Example 39 includes the subject matter of any of Examples 28-38, andwherein the means for generating the output indicative of whether theelement satisfied the set membership query condition comprises means forpacking extracted one-bit values until a width of the extracted one-bitvalues matches a data path width.

1-27. (canceled)
 28. A computing device for determining set membership,the computing device comprising one or more accelerator devices, eachaccelerator device is to: receive input data and definition tableconfiguration data, the input data including a packed array of unsignedintegers of column data from database and the definition tableconfiguration data including a set membership query condition; generate,in response to receiving the definition table configuration data, adefinition table indicative of element values that satisfy the setmembership query condition; generate a lookup request for an element ofthe column data of the input data; perform the lookup request byaccessing the definition table to determine whether the elementsatisfies the set membership query condition; and generate an outputindicative of whether the element is a member of the set membership. 29.The computing device of claim 28, wherein the each accelerator device isfurther to determine a number of elements to be processed in each cyclebased on based on an element width of the input data and a data pathwidth of the accelerator device.
 30. The computing device of claim 28,wherein the each accelerator device is further to: decompress, inresponse to receiving the input data, the input data; and pre-process,in response to decompressing the input data, the decompressed inputdata.
 31. The computing device of claim 30, wherein to pre-process thedecompressed input data comprises to align elements of the column dataof the input data based on a width of elements of the decompressed inputdata and to prepend zeroes to match a data path width.
 32. The computingdevice of claim 28, wherein to generate the definition table comprisesto generate a set membership bit vector with one or more predicate bitsindicative of set membership.
 33. The computing device of claim 32,wherein to generate the definition table comprises to: determine whethera width of each element in the input data exceeds a threshold;construct, in response to a determination that the width of elementsexceeds the threshold, a large definition table to store the setmembership bit vector; and construct, in response to a determinationthat the width of elements does not exceed the threshold, a smalldefinition table to store the set membership bit vector.
 34. Thecomputing device of claim 28, wherein the definition table supportsparallel accesses by duplicating the definition table.
 35. The computingdevice of claim 28, wherein the definition table supports parallelaccesses by implementing multiple read ports.
 36. The computing deviceof claim 32, wherein to perform the lookup request comprises to performthe lookup request by accessing the definition table to determinewhether the element matches at least one predicate bit of the setmembership bit vector.
 37. The computing device of claim 33, wherein toperform the lookup request comprises to: determine whether a width ofthe element exceeds a threshold; access, in response to a determinationthat the width of the element exceeds the threshold, the largedefinition table to determine whether the element satisfies the setmembership query condition; and access, in response to a determinationthat the width of the element does not exceed the threshold, the smalldefinition table to determine whether the element satisfies the setmembership query condition.
 38. The computing device of claim 28,wherein to generate the output indicative of whether the elementsatisfied the set membership query condition comprises to extract aone-bit value indicating whether the element satisfies the setmembership query condition.
 39. The computing device of claim 38,wherein to generate the output indicative of whether the elementsatisfied the set membership query condition comprises to pack extractedone-bit values until a width of the extracted one-bit values matches adata path width.
 40. One or more machine-readable storage mediacomprising a plurality of instructions stored thereon that, in responseto being executed, cause a computing device to: receive input data anddefinition table configuration data, the input data including a packedarray of unsigned integers of column data from database and thedefinition table configuration data including a set membership querycondition; generate, in response to receiving the definition tableconfiguration data, a definition table indicative of element values thatsatisfy the set membership query condition; generate a lookup requestfor an element of the column data of the input data; perform the lookuprequest by accessing the definition table to determine whether theelement satisfies the set membership query condition; and generate anoutput indicative of whether the element is a member of the setmembership.
 41. The one or more machine-readable storage media of claim40, further comprising a plurality of instructions that in response tobeing executed cause the computing device to determine a number ofelements to be processed in each cycle based on based on an elementwidth of the input data and a data path width of the accelerator device.42. The one or more machine-readable storage media of claim 40, furthercomprising a plurality of instructions that in response to beingexecuted cause the computing device to: decompress, in response toreceiving the input data, the input data; and pre-process, in responseto decompressing the input data, the decompressed input data.
 43. Theone or more machine-readable storage media of claim 40, wherein togenerate the definition table comprises to generate a set membership bitvector with one or more predicate bits indicative of set membership. 44.The one or more machine-readable storage media of claim 43, wherein togenerate the definition table comprises to: determine whether a width ofeach element in the input data exceeds a threshold; construct, inresponse to a determination that the width of elements exceeds thethreshold, a large definition table to store the set membership bitvector; and construct, in response to a determination that the width ofelements does not exceed the threshold, a small definition table tostore the set membership bit vector.
 45. The one or moremachine-readable storage media of claim 43, wherein to perform thelookup request comprises to perform the lookup request by accessing thedefinition table to determine whether the element matches at least onepredicate bit of the set membership bit vector.
 46. The one or moremachine-readable storage media of claim 44, wherein to perform thelookup request comprises to: determine whether a width of the elementexceeds a threshold; access, in response to a determination that thewidth of the element exceeds the threshold, the large definition tableto determine whether the element satisfies the set membership querycondition; and access, in response to a determination that the width ofthe element does not exceed the threshold, the small definition table todetermine whether the element satisfies the set membership querycondition.
 47. A method for determining set membership by a computingdevice, the method comprising: receiving, by an accelerator of thecomputing device, input data and definition table configuration data,the input data including a packed array of unsigned integers of columndata from database and the definition table configuration data includinga set membership query condition; generating, in response to receivingthe definition table configuration data and by the accelerator, adefinition table indicative of element values that satisfy the setmembership query condition; generating, by the accelerator, a lookuprequest for an element of the column data of the input data; performing,by the accelerator, the lookup request by accessing the definition tableto determine whether the element satisfies the set membership querycondition; and generating, by the accelerator, an output indicative ofwhether the element is a member of the set membership.
 48. The method ofclaim 47 further comprising: decompressing, by the accelerator and inresponse to importing the input data, the input data; andpre-processing, by the accelerator and in response to decompressing theinput data, the decompressed input data.
 49. The method of claim 47,wherein generating the definition table comprises generating, by theaccelerator, a set membership bit vector with one or more predicate bitsindicative of set membership.
 50. The method of claim 49, whereingenerating the definition table based on the definition tableconfiguration data comprises: determining, by the accelerator, whether awidth of each element in the input data exceeds a threshold;constructing, in response to a determination that the width of elementsexceeds the threshold, a large definition table to store the setmembership bit vector; and constructing, in response to a determinationthat the width of elements does not exceed the threshold, a smalldefinition table to store the set membership bit vector.
 51. The methodof claim 49, wherein performing the lookup request comprises performing,by the accelerator, the lookup request by accessing the definition tableto determine whether the element matches at least one predicate bit ofthe set membership bit vector.
 52. The method of claim 50, whereinperforming the lookup request by accessing the definition table todetermine whether the element satisfies the set membership querycondition comprises: determining, by the accelerator, whether a width ofthe element exceeds a threshold; accessing, in response to adetermination that the width of the element exceeds the threshold and bythe accelerator, the large definition table to determine whether theelement satisfies the set membership query condition; and accessing, inresponse to a determination that the width of the element does notexceed the threshold and by the accelerator, the small definition tableto determine whether the element satisfies the set membership querycondition.